TMS320DM6441
TMS320DM6441 is Digital Media System-on-Chip DMSoC manufactured by Texas Instruments.
Features
- High-Performance Digital Media So C
- C64x+™ DSP Clock Rate
- 405-MHz (Max) at 1.05 V or 513-MHz (Max) at 1.2 V
- ARM926EJ-S™ Clock Rate
- 202.5-MHz (Max) at 1.05 V or 256-MHz (Max) at 1.2 V
- Eight 32-Bit C64x+ Instructions/Cycle
- 4752 C64x+ MIPS
- Fully Software-patible With C64x / ARM9™
- Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
- Eight Highly Independent Functional Units
- Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
- Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
- Load-Store Architecture With Non-Aligned Support
- 64 32-Bit General-Purpose Registers
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Additional C64x+™ Enhancements
- Protected Mode Operation
- Exceptions Support for Error Detection and Program Redirection
- Hardware Support for Modulo Loop Operation
- C64x+ Instruction Set Features
- Byte-Addressable (8-/16-/32-/64-Bit Data)
- 8-Bit Overflow Protection
- Bit-Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- pact 16-Bit Instructions
- Additional Instructions to Support plex Multiplies
- C64x+ L1/L2 Memory Architecture
- 32K-Byte L1P Program RAM/Cache (Direct Mapped)
- 80K-Byte L1D Data RAM/Cache (2-Way Set-Associative)
- 64K-Byte L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
- ARM926EJ-S Core
- Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets
- DSP Instruction Extensions and Single Cycle MAC
- ARM® Jazelle® Technology
- Embedded ICE-RT™ Logic for Real-Time Debug
- ARM9 Memory Architecture
- 16K-Byte Instruction...
