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TMS417800 Datasheet Preview

TMS417800 Datasheet

HIGH-SPEED DRAMS

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TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
D Organization . . . 2 097152 × 8
D Single 5 V Power Supply (±10% Tolerance)
D Performance Ranges:
ACCESS ACCESS ACCESS READ OR
TIME TIME TIME WRITE
tRAC
MAX
tCAC
MAX
tAA CYCLE
MAX MIN
’41x800-60
60 ns 15 ns 30 ns 110 ns
’41x800-70
70 ns 18 ns 35 ns 130 ns
’41x800-80
80 ns 20 ns 40 ns 150 ns
D Enhanced Page-Mode Operation With
CAS-Before-RAS ( CBR) Refresh
D High-Impedance State Unlatched Output
D High-Reliability Plastic 28-Lead
400-Mil-Wide Surface-Mount Small-Outline
J-Lead (SOJ) Package
D Operating Free-Air Temperature Range
0°C to 70°C
D Fabricated Using Enhanced Performance
Implanted CMOS (EPIC) Technology by
Texas Instruments (TI)
description
The TMS41x800 series is a set of high-speed,
16 777 216-bit dynamic random-access memo-
ries (DRAMs) organized as 2 097 152 words of
eight bits each. It employs TI’s state-of-the-art
EPIC technology for high performance, reliability,
and low power.
These devices feature maximum RAS access
times of 60 ns, 70 ns, and 80 ns. All addresses and
data-in lines are latched on-chip to simplify
system design. Data out is unlatched to allow
greater system flexibility.
The TMS416800 and TMS417800 are offered in
a 28-lead plastic surface-mount SOJ package
(DZ suffix). This package is characterized for
operation from 0°C to 70°C.
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
DZ PACKAGE
( TOP VIEW )
VCC
DQ0
DQ1
DQ2
DQ3
W
RAS
A11
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VSS
27 DQ7
26 DQ6
25 DQ5
24 DQ4
23 CAS
22 OE
21 A9
20 A8
19 A7
18 A6
17 A5
16 A4
15 VSS
PIN NOMENCLATURE
A0 – A11†
CAS
DQ0 – DQ7
OE
RAS
VCC
VSS
W
Address Inputs
Column-Address Strobe
Data In / Data Out
Output Enable
Row-Address Strobe
5V
Ground
Write Enable
A11 is NC (no internal connection) for TMS417800.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and TI are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1996, Texas Instruments Incorporated
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
1




etcTI

TMS417800 Datasheet Preview

TMS417800 Datasheet

HIGH-SPEED DRAMS

No Preview Available !

TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
operation
enhanced page mode
Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. The time for row-address setup and hold and address multiplex is eliminated. The
maximum number of columns that can be accessed is determined by tRASP , the maximum row-address strobe
(RAS) low time.
Unlike conventional page-mode DRAMs, the column-address buffers in these devices are activated on the
falling edge of RAS. The buffers act as transparent or flow-through latches while column-address strobe (CAS)
is high. The falling edge of CAS latches the column addresses and enables the output. This feature allows the
devices to operate at a higher data bandwidth than conventional page-mode parts because data retrieval begins
as soon as the column address is valid rather than when CAS goes low. This performance improvement is
referred to as enhanced page mode. A valid column address can be presented immediately after row-address
hold time has been satisfied, usually well in advance of the falling edge of CAS. In this case, data is obtained
after tCAC max (access time from CAS low) if tAA max (access time from column address) and tRAC (access time
from RAS) have been satisfied. In the event that column address for the next cycle is valid at the time CAS goes
high, access time for the next cycle is determined by the later occurrence of tCPA (access time from CAS
precharge) or tCAC.
address: A0 – A11 ( TMS416800) and A0 – A10 (TMS417800)
Twenty-one address bits are required to decode one of 2 097 152 storage cell locations. For the TMS416800,
12 row-address bits are set up on A0 through A11 and latched on the chip by the RAS. Nine column-address
bits are set up on A0 through A8. For the TMS417800, 11 row-address bits are set up on inputs A0 through A10
and latched on the chip by RAS. Ten column-address bits are set up on A0 through A9. All addresses must be
stable on or before the falling edges of RAS and CAS. RAS is similar to a chip enable because it activates the
sense amplifiers as well as the row decoder. CAS is used as a chip select, activating the output buffers and
latching the address bits into the column-address buffers.
write enable ( W)
The read or write mode is selected through W. A logic high on W selects the read mode, and a logic low selects
the write mode. The data inputs are disabled when the read mode is selected. When W goes low prior to CAS
(early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with
OE grounded.
data in (DQ0 – DQ7)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge
of CAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to CAS, and
the data is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or
read-modify-write cycle, CAS is already low, and the data is strobed in by W with setup and hold time referenced
to this signal. In a delayed-write or read-modify-write cycle, OE must be high to bring the output buffers to the
high-impedance state prior to impressing data on the I/O lines.
data out (DQ0 – DQ7)
Data out is the same polarity as data in. The output is in the high-impedance (floating) state until CAS and OE
are brought low. In a read cycle, the output becomes valid after the access time interval tCAC (which begins with
the negative transition of CAS) as long as tRAC and tAA are satisfied.
2 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443


Part Number TMS417800
Description HIGH-SPEED DRAMS
Maker etcTI
Total Page 25 Pages
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