2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
extended data out
Extended data out (EDO) allows data output rates up to 40 MHz for 60-ns devices. When keeping the same
row address while selecting random column addresses, the time for row-address setup and hold, and for
address multiplex is eliminated. The maximum number of columns that can be accessed is determined by
tRASP , the maximum RAS low time.
Extended data out does not place the data in / data out pins (DQs) into the high-impedance state with the rising
edge of CAS. The output remains valid for the system to latch the data. After CAS goes high, the DRAM decodes
the next address. OE and W can control the output impedance. Descriptions of OE and W further explain EDO
address: A0 – A11 ( TMS416809) and A0 – A10 (TMS417809)
Twenty-one address bits are required to decode 1 of 2 097 152 storage-cell locations. For the TMS416809,
12 row-address bits are set up on A0 through A11 and latched onto the chip by the row-address strobe (RAS).
Nine column-address bits are set up on A0 through A8. For the TMS417809, 11 row-address bits are set up on
inputs A0 through A10 and latched onto the chip by RAS. Ten column-address bits are set up on A0 through
A9. All addresses must be stable on or before the falling edge of RAS and CAS. RAS is similar to a chip enable
because it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select, activating
the output buffers and latching the address bits into the column-address buffers.
output enable (OE)
OE controls the impedance of the output buffers. While CAS and RAS are low and W is high, OE can be brought
low or high and the DQs transition between valid data and high impedance (see Figure 7). There are two
methods for placing the DQs into the high-impedance state and maintaining that state during CAS high time.
The first method is to transition OE high before CAS transitions high and keep OE high for tCHO (hold time, OE
from CAS) past the CAS transition. This disables the DQs and they remain disabled, regardless of OE, until CAS
falls again. The second method is to have OE low as CAS transitions high. Then OE can pulse high for a
minimum of tOEP (precharge time, OE) anytime during CAS high time, disabling the DQs regardless of further
transitions on OE until CAS falls again (see Figure 7).
write enable ( W)
The read or write mode is selected through W. A logic high on W selects the read mode, and a logic low selects
the write mode. The data inputs are disabled when the read mode is selected. When W goes low prior to CAS
(early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with
OE grounded. If W goes low in an extended-data-out read cycle, the DQs are disabled so long as CAS is high
(see Figure 8).
data in / data out (DQ0 – DQ7)
Data is written during a write or a read-modify-write cycle. Depending on the mode of operation, the later falling
edge of CAS or W strobes data into the on-chip data latch with setup and hold times referenced to the later edge.
The DQs drive valid data after all access times are met and remain valid except in cases described in the W
and OE descriptions.
A refresh operation must be performed at least once every 64 ms to retain data. This can be achieved by strobing
each of the 4 096 rows (A0 – A11). A normal read or write cycle refreshes all bits in each row that is selected.
A RAS-only operation can be used by holding CAS at the high (inactive) level, conserving power as the output
buffers remain in the high-impedance state. Externally generated addresses must be used for a RAS-only
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