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TMS427809AP Datasheet Preview

TMS427809AP Datasheet

DYNAMIC RANDOM-ACCESS MEMORIES

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TMS417809A, TMS427809A, TMS427809AP
2097152 BY 8-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS894B – AUGUST 1996 – REVISED NOVEMBER 1997
This data sheet is applicable to all
TMS417809As and TMS427809A/Ps
symbolized by Revision “E” and subsequent
revisions as described in the device
symbolization section.
D Organization . . . 2 097152 by 8 Bits
D Single Power Supply (5 V or 3.3 V)
D Performance Ranges:
’417809A-50
’417809A-60
ACCESS ACCESS ACCESS
TIME TIME TIME
tRAC
MAX
tCAC
MAX
tAA
MAX
50 ns 13 ns 25 ns
60 ns 15 ns 30 ns
EDO
CYCLE
tHPC
MIN
20 ns
25 ns
’417809A-70
70 ns
’427809A/P-50 50 ns
18 ns
13 ns
35 ns
25 ns
30 ns
20 ns
’427809A/P-60 60 ns 15 ns 30 ns
25 ns
’427809A/P-70 70 ns 18 ns 35 ns
30 ns
D Extended-Data-Out (EDO) Operation
D CAS-Before-RAS ( CBR) Refresh
D Long Refresh Period and Self-Refresh
Option (TMS427809AP)
D High-Impedance State Unlatched Output
D High-Reliability Plastic 28-Lead
400-Mil-Wide Surface-Mount Small-Outline
J-Lead (SOJ) Package (DZ Suffix) and
28-Lead 400-Mil-Wide Surface-Mount Thin
Small-Outline Package (TSOP) (DGC Suffix)
D Ambient Temperature Range
0°C to 70°C
DZ / DGC PACKAGE
( TOP VIEW )
VCC
DQ0
DQ1
DQ2
DQ3
W
RAS
NC
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VSS
27 DQ7
26 DQ6
25 DQ5
24 DQ4
23 CAS
22 OE
21 A9
20 A8
19 A7
18 A6
17 A5
16 A4
15 VSS
A[0 :10]
DQ[0: 7]
CAS
NC
OE
RAS
VCC
VSS
W
PIN NOMENCLATURE
Address Inputs
Data In / Data Out
Column-Address Strobe
No Internal Connection
Output Enable
Row-Address Strobe
3.3-V or 5-V Supply
Ground
Write Enable
description
The TMS417809A and TMS427809A series are
16 777 216-bit dynamic random access memory
(DRAM) devices organized as 2 097 152 words of
8 bits each. The TMS427809AP series is a
low-power, self-refresh, 16 777 216-bit DRAM
organized as 4 194 304 words of four bits.They
employ TI state-of-the-art technology for high
performance, reliability, and low power.
AVAILABLE OPTIONS
DEVICE
POWER
SUPPLY
REFRESH
CYCLES
TMS417809A
5 V 2 048 in 32 ms
TMS427809A
3.3 V
2 048 in 32 ms
TMS427809AP
3.3 V
2 048 in 128 ms
These devices feature maximum RAS access times of 50-, 60-, and 70 ns. All address and data-in lines are
latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The TMS417809A is offered in a 28-lead plastic surface-mount SOJ package (DZ suffix). The TMS427809A / P
is offered in a 28-lead plastic surface-mount TSOP package (DGC suffix). These packages are designed for
operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1997, Texas Instruments Incorporated
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
1




etcTI

TMS427809AP Datasheet Preview

TMS427809AP Datasheet

DYNAMIC RANDOM-ACCESS MEMORIES

No Preview Available !

TMS417809A, TMS427809A, TMS427809AP
2097152 BY 8-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS894B – AUGUST 1996 – REVISED NOVEMBER 1997
logic symbol (TMS417809A and TMS427809A/P)
A0 10
A1 11
A2 12
A3 13
A4 16
A5 17
A6 18
A7 19
A8 20
A9 21
A10 9
RAS 7
CAS 23
W6
RAM 2M x 8
20D10/21D0
A
2
0
097
151
20D19/21D9
20D20
C20[ROW]
G23/[REFRESH ROW]
24[PWR DWN]
C21[COL]
G24
&
23C22
23,21D
24,25EN
OE 22
DQ0 2
DQ1 3
DQ2 4
DQ3 5
DQ4 24
DQ5 25
DQ6 26
DQ7 27
G25
A,22D
26
A,Z26
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 647-12.
2 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443


Part Number TMS427809AP
Description DYNAMIC RANDOM-ACCESS MEMORIES
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Total Page 29 Pages
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