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TPIC5323L - logic-level power DMOS array

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General Description

DRAIN3 6 11 SOURCE3 The TPIC5323L is a monolithic gate-protected logic-level power DMOS array that consists of DRAIN3 7 GND 8 10 SOURCE3 9 GATE3 three electrically isolated independent N-channel enhancement-mode DMOS transistors.

Each transistor

Overview

TPIC5323L 3-CHANNEL INDEPENDENT GATE-PROTECTED LOGIC-LEVEL POWER DMOS ARRAY SLIS044A – NOVEMBER 1994 – REVISED SEPTEMBER 1995 D Low rDS(on) .

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Key Features

  • integrated high-current zener diodes (ZCXa and ZCXb) to prevent gate damage in the event that an overstress condition occurs. These zener diodes also provide up to 4000 V of ESD protection when tested using the human-body model of a 100-pF capacitor in series with a 1.5-kΩ resistor. The TPIC5323L is offered in a standard 16-pin small-outline surface-mount (D) package and is characterized for operation over the case temperature of.
  • 40°C to 125°C. schematic DRAIN1 12, 13 GATE2 5 DRA.

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