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TPIC6A259 - POWER LOGIC 8-BIT ADDRESSABLE LATCH

Description

This power logic 8-bit addressable latch controls open-drain DMOS-transistor outputs and is designed for general-purpose storage applications in digital systems.

Specific uses include working registers, serial-holding registers, and decoders or demultiplexers.

Features

  • an independent chopping current-limiting circuit to prevent damage in the case of a short circuit. Four distinct modes of operation are selectable by controlling the clear (CLR) and enable (G) inputs as enumerated in the function table. In the addressable-latch mode, data at the data-in (D) terminal is written into the addressed latch. The addressed DMOS-transistor output inverts the data input with all unaddressed DMOS-transistor outputs remaining in their previous states. In the memory mode, a.

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Full PDF Text Transcription

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ą • Low rDS(on) . . . 1 Ω Typ • Output Short-Circuit Protection • Avalanche Energy . . . 75 mJ • Eight 350-mA DMOS Outputs • 50-V Switching Capability • Four Distinct Function Modes • Low Power Consumption description This power logic 8-bit addressable latch controls open-drain DMOS-transistor outputs and is designed for general-purpose storage applications in digital systems. Specific uses include working registers, serial-holding registers, and decoders or demultiplexers. This is a multifunctional device capable of operating as eight addressable latches or an 8-line demultiplexer with active-low DMOS outputs. Each open-drain DMOS transistor features an independent chopping current-limiting circuit to prevent damage in the case of a short circuit.
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