TPIC6A596 Datasheet | Texas Instruments

tion SRCK 8 DRAIN4 9 13 SER OUT 12 DRAIN7 The TPIC6A596 is a monolithic, high-voltage, DRAIN5 10 11 DRAIN6 high-current power logic 8-bit shift register designed for use in systems that require relatively high load power. The device contains a built-in DW PACKAGE (TOP VIEW) voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids, and other mediumcurrent or high-voltage loads. Each open-drain DMOS transistor Features an independent chopping current-limiting circuit to prevent damage in the case of a short circuit. This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit, D-type storage register. Data transfers through both the shift and storage registers on the rising edge of the shiftregister clock (SRCK) and the register clock (RCK), respectively. The storage register DRAIN2 1 DRAIN3 2 SRCLR 3 G4 PGND 5 PGND 6 PGND 7 PGND 8 RCK 9 SRCK 10 DRAIN4 11 DRAIN5 12 24 DRAIN1 23 DRAIN0 22 SER IN 21 VCC 20 PGND 19 PGND 18 PGND 17 PGND 16 LGND 15 SER OUT 14 DRAIN7 13 DRAIN6 transfers data to the output buffer when shift- register clear (SRCLR) is high. When SRCLR is low, all registers in the device are cleared. When output enable G is held high, all data in the output buffers is held low and all drain outputs are off. When G is held low, data from the storage register is transparent to the output buffers. The serial output (SER OUT) is clocked out of the device on the falling edge of SRCK to provide additional hold time for cascaded applications. This will provide improved performance for applications where clock signals may be skewed, devices are not located near one another, or the system must tolerate electromagnetic interference. Outputs are low-side, open-drain DMOS transistors with output ratings of 50 V and a 350-m A continuous sink current capability. When data in the output buffers is low, the DMOS-transistor outputs are off. When data is high, the...