TPIC6259 Datasheet | Texas Instruments

description DRAIN3 7 S1 8 14 DRAIN4 13 G This power logic 8-bit addressable latch controls open-drain DMOS transistor outputs and is LGND 9 PGND 10 12 S2 11 PGND designed for general-purpose storage applications in digital systems. Specific uses include working registers, serial-holding registers, and decoders or demultiplexers. This is a multifunctional device capable of storing single-line data in eight addressable latches with 3-to-8 INPUTS CLR G D H LH HLL FUNCTION TABLE OUTPUT OF ADDRESSED DRAIN EACH OTHER DRAIN Qio Qio FUNCTION Addressable Latch decoding or demultiplexing mode active-low DMOS outputs. Four distinct modes of operation are selectable by controlling the clear (CLR) and enable (G) inputs H HX Qio L LH L LL L HX Qio Memory 8-Line Demultiplexer Clear as enumerated in the function table. In the addressable-latch mode, data at the data-in (D) LATCH SELECTION TABLE terminal is written into the addressed latch. The addressed DMOS transistor output inverts the SELECT INPUTS DRAIN S2 S1 S0 ADDRESSED data input with all unaddressed DMOS-transistor outputs remaining in their previous states. In the memory mode, all DMOS-transistor outputs remain in their previous states and are unaffected by the data or address inputs. To eliminate the possibility of entering erroneous data in the latch, enable G should be held high (inactive) while the LL L LH...