TPIC6596 Datasheet | Texas Instruments

description DW OR N PACKAGE (TOP VIEW) PGND 1 VCC 2 SER IN 3 DRAIN0 4 DRAIN1 5 DRAIN2 6 DRAIN3 7 SRCLR 8 G9 PGND 10 20 PGND 19 LGND 18 SER OUT 17 DRAIN7 16 DRAIN6 15 DRAIN5 14 DRAIN4 13 SRCK 12 RCK 11 PGND The TPIC6596 is a monolithic, high-voltage, highcurrent power 8-bit shift register designed for use logic symbol† in systems that require relatively high load power. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids, and other medium-current or high-voltage loads. G9 RCK 12 8 SRCLR 13 SRCK EN3 C2 SRG8 R C1 This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Data transfers through both the shift and storage registers on the rising edge of the shift-register clock (SRCK) and the register clock (RCK) respectively. The storage register transfers data to the output buffer when shift-register clear (SRCLR) is high. When SRCLR is low, all registers in the device are cleared. When output enable (G) is held high, all data in the output buffers is held low and all drain outputs are off. SER IN 3 1D DRAIN0 5 DRAIN1 6 DRAIN2 7 DRAIN3 14 DRAIN4 15 DRAIN5 16 DRAIN6 DRAIN7 SER OUT When G is held low, data from the storage register is transparent to the output buffers. The serial output (SER OUT) is clocked out of the device on † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. the falling edge of SRCK to provide additional hold time for cascaded applications. This will provide improved performance for applications where clock signals may be skewed, devices are not located near one another, or the system must tolerate electromagnetic interference. Outputs are low-side, open-drain DMOS transistors with output ratings of 45 V and 250-m A continuous sink current capability. When data in the output buffers is low, the DMOS-transistor outputs are off....