TPS53317A Overview
The TPS53317A device is a FET-integrated synchronous buck regulator designed mainly for DDR termination. It can provide a regulated output at ½ VDDQ with both sink and source capability. The TPS53317A device employs D-CAP+ mode operation that provides ease of use, low external ponent count and fast transient response.
TPS53317A Key Features
- 1 TI-Proprietary Integrated MOSFET and Packaging Technology
- Supports DDR Memory Termination with up to 6-A Continuous Output Source or Sink Current
- External Tracking
- Minimum External ponents Count
- 0.9-V to 6-V Conversion Voltage
- D-CAP+™ Mode Architecture
- Supports All MLCC Output Capacitors and
- Selectable SKIP Mode or Forced CCM
- Optimized Efficiency at Light and Heavy Loads
- Selectable 600-kHz or 1-MHz Switching
TPS53317A Applications
- Memory Termination Regulator for DDR, DDR2, DDR3, DDR3L, and DDR4