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74AHC273BQ - Octal D-type flip-flop

Download the 74AHC273BQ datasheet PDF. This datasheet also covers the 74AHC273 variant, as both devices belong to the same octal d-type flip-flop family and are provided as variant models within a single manufacturer datasheet.

Description

The 74AHC273; 74AHCT273 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL).

It is specified in compliance with JEDEC standard No.

7-A.

Features

  • Balanced propagation delays.
  • All inputs have Schmitt-trigger actions.
  • Inputs accept voltages higher than VCC.
  • Ideal buffer for MOS microcontroller or memory.
  • Common clock and master reset.
  • Input levels:.
  • For 74AHC273: CMOS level.
  • For 74AHCT273: TTL level.
  • ESD protection:.
  • HBM JESD22-A114E exceeds 2000 V.
  • MM JESD22-A115-A exceeds 200 V.
  • CDM JESD22-C101C exceeds 1000 V.
  • Multiple p.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74AHC273-nexperia.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
74AHC273 Octal D-type flip-flop NXP
74AHC244 Octal buffer/line driver NXP
74AHC244-Q100 Octal buffer/line driver NXP
74AHC245 Octal bus transceiver NXP
74AHC257 Quad 2-input multiplexer NXP

Other Datasheets by Nexperia

Part Number Description
74AHC273 Octal D-type flip-flop
74AHC273-Q100 Octal D-type flip-flop
74AHC273D Octal D-type flip-flop
74AHC273PW Octal D-type flip-flop
74AHC244 Octal buffer/line driver

Full PDF Text Transcription

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74AHC273; 74AHCT273 Octal D-type flip-flop with reset; positive-edge trigger Rev. 4 — 23 September 2020 Product data sheet 1. General description The 74AHC273; 74AHCT273 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC273; 74AHCT273 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs, load and reset (clear) all flip-flops simultaneously. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. All outputs will be forced LOW, independent of clock or data inputs, by a LOW on the MR input.
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