74AHC273 Datasheet | NXP Semiconductors

INTEGRATED CIRCUITS DATA SHEET 74AHC273; 74AHCT273 Octal D-type flip-flop with reset; positive-edge trigger Product specification File under Integrated Circuits, IC06 1999 Sep 01 Philips Semiconductors Product specification Octal D-type flip-flop with reset; positive-edge trigger Features - Ideal buffer for MOS microcontroller or memory - mon clock and master reset - ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V - Balanced propagation delays - All inputs have Schmitt trigger actions - Inputs accepts voltages higher than VCC - See ‘377’ for clock enable version - See ‘373’ for transparent latch version - See ‘374’ for 3-state version - For AHC only: operates with CMOS input levels - For AHCT only: operates with TTL input levels - Specified from - 40 to +85 °C and - 40 to +125 °C. QUICK REFERENCE DATA Ground = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns. DESCRIPTION 74AHC273; 74AHCT273 The 74AHC/AHCT273 are high-speed Si-gate CMOS devices and are pin patible with low power Schottky TTL (LSTTL). They are specified in pliance with JEDEC standard no. 7A. The 74AHC/AHCT273 have eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The mon clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. All outputs will be forced LOW independently of clock or data inputs by a LOW on the MR input. The device is useful for applications where the true output only is required and the clock and master reset are mon to all storage elements. TYPICAL SYMBOL t PHL/t PLH PARAMETER propagation delay CP to Qn MR to Qn fmax CI CO CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output...