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74AHC273PW Datasheet Preview

74AHC273PW Datasheet

Octal D-type flip-flop

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74AHC273; 74AHCT273
Octal D-type flip-flop with reset; positive-edge trigger
Rev. 4 — 23 September 2020
Product data sheet
1. General description
The 74AHC273; 74AHCT273 is a high-speed Si-gate CMOS device and is pin compatible with
Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.
The 74AHC273; 74AHCT273 has eight edge-triggered, D-type flip-flops with individual D inputs
and Q outputs. The common clock (CP) and master reset (MR) inputs, load and reset (clear) all
flip-flops simultaneously. The state of each D input, one set-up time before the LOW-to-HIGH clock
transition, is transferred to the corresponding output (Qn) of the flip-flop. All outputs will be forced
LOW, independent of clock or data inputs, by a LOW on the MR input.
The device is useful for applications where only the true output is required and the clock and
master reset are common to all storage elements.
2. Features
Balanced propagation delays
All inputs have Schmitt-trigger actions
Inputs accept voltages higher than VCC
Ideal buffer for MOS microcontroller or memory
Common clock and master reset
Input levels:
For 74AHC273: CMOS level
For 74AHCT273: TTL level
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
74AHC273D
74AHCT273D
-40 °C to +125 °C SO20
plastic small outline package; 20 leads;
body width 7.5 mm
74AHC273PW
74AHCT273PW
-40 °C to +125 °C TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
74AHC273BQ
74AHCT273BQ
-40 °C to +125 °C
DHVQFN20 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 20 terminals;
body 2.5 × 4.5 × 0.85 mm
Version
SOT163-1
SOT360-1
SOT764-1




nexperia

74AHC273PW Datasheet Preview

74AHC273PW Datasheet

Octal D-type flip-flop

No Preview Available !

Nexperia
4. Functional diagram
11
CP
3 D0
Q0 2
4 D1
Q1 5
7 D2
Q2 6
8 D3
Q3 9
13 D4
Q4 12
14 D5
Q5 15
17 D6
Q6 16
18 D7
Q7 19
MR
1 mna763
Fig. 1. Logic symbol
D0
74AHC273; 74AHCT273
Octal D-type flip-flop with reset; positive-edge trigger
CP 11
C1
MR 1
R
D0 3 1D
D1 4
D2 7
D3 8
D4 13
D5 14
D6 17
D7 18
Fig. 2. IEC logic symbol
mna764
2 Q0
5 Q1
6 Q2
9 Q3
12 Q4
15 Q5
16 Q6
19 Q7
D1
D2
D3
DQ
CP
FF1
RD
DQ
CP
FF2
RD
DQ
CP
FF3
RD
DQ
CP
FF4
RD
CP
MR
Q0
Q1
Q2
Q3
D4
D5
D6
D7
DQ
CP
FF5
RD
DQ
CP
FF6
RD
DQ
CP
FF7
RD
DQ
CP
FF8
RD
Fig. 3. Logic diagram
74AHC_AHCT273
Product data sheet
Q4
Q5
Q6
Q7
001aae056
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 23 September 2020
© Nexperia B.V. 2020. All rights reserved
2 / 16


Part Number 74AHC273PW
Description Octal D-type flip-flop
Maker nexperia
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74AHC273PW Datasheet PDF






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