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74AHC377PW - Octal D-type flip-flop

This page provides the datasheet information for the 74AHC377PW, a member of the 74AHC377 Octal D-type flip-flop family.

Datasheet Summary

Description

The 74AHC377; 74AHCT377 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL).

It is specified in compliance with JEDEC standard No.

7-A.

Features

  • I Balanced propagation delays I All inputs have Schmitt-trigger actions I Inputs accept voltages higher than VCC I Ideal for addressable register.

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Datasheet preview – 74AHC377PW

Datasheet Details

Part number 74AHC377PW
Manufacturer nexperia
File Size 584.98 KB
Description Octal D-type flip-flop
Datasheet download datasheet 74AHC377PW Datasheet
Additional preview pages of the 74AHC377PW datasheet.

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Full PDF Text Transcription

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74AHC377; 74AHCT377 Octal D-type flip-flop with data enable; positive-edge trigger Rev. 02 — 12 June 2008 Product data sheet 1. General description The 74AHC377; 74AHCT377 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC377; 74AHCT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. A common clock input (CP) loads all flip-flops simultaneously when the data enable input (E) is LOW. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. The E input is only required to be stable one set-up time prior to the LOW-to-HIGH transition for predictable operation.
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