74AHC377PW
description
The 74AHC377; 74AHCT377 is a high-speed Si-gate CMOS device and is pin patible with Low-power Schottky TTL (LSTTL). It is specified in pliance with JEDEC standard No. 7-A.
The 74AHC377; 74AHCT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. A mon clock input (CP) loads all flip-flops simultaneously when the data enable input (E) is LOW. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. The E input is only required to be stable one set-up time prior to the LOW-to-HIGH transition for predictable operation.
For versions associated with the 74AHC377; 74AHCT377, refer to the following:
- For the master reset version, see 74AHC273; 74AHCT273
- For the transparent latch version, see 74AHC373; 74AHCT373
- For the 3-state version, see 74AHC374; 74AHCT374
2. Features
I Balanced propagation delays I All inputs have Schmitt-trigger actions I Inputs accept...
