74AHC74PW Datasheet - nexperia

Dual D-type flip-flop

74AHC74PW Features

* Balanced propagation delays

* All inputs have Schmitt-trigger actions

* Inputs accept voltages higher than VCC

* Input levels:

* For 74AHC74: CMOS level

* For 74AHCT74: TTL level

* ESD protection:

* HBM EIA/JESD22-A114E exceeds 2000 V

74AHC74PW General Description

The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC74; 74AHCT74 is a dual positive-edge triggered, D-type flip-flop with individual data inputs (D), clock inputs (CP).

74AHC74PW Datasheet (251.31 KB)

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Datasheet Details

Part number:

74AHC74PW

Manufacturer:

nexperia ↗

File Size:

251.31 KB

Description:

Dual d-type flip-flop.
74AHC74; 74AHCT74 Dual D-type flip-flop with set and reset; positive-edge trigger Rev. 8 22 April 2020 Product data sheet 1. General des.

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74AHC74PW Dual D-type flip-flop nexperia

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74AHC74PW Features

74AHC74PW General Description

Datasheet Details

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Description:

74AHC74PW Distributor