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74AHC74PW - Dual D-type flip-flop

Download the 74AHC74PW datasheet PDF (74AHC74 included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for dual d-type flip-flop.

Description

The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL).

It is specified in compliance with JEDEC standard No.

7-A.

Features

  • Balanced propagation delays.
  • All inputs have Schmitt-trigger actions.
  • Inputs accept voltages higher than VCC.
  • Input levels:.
  • For 74AHC74: CMOS level.
  • For 74AHCT74: TTL level.
  • ESD protection:.
  • HBM EIA/JESD22-A114E exceeds 2000 V.
  • MM EIA/JESD22-A115-A exceeds 200 V.
  • CDM EIA/JESD22-C101C exceeds 1000 V.
  • Multiple package options.
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74AHC74-nexperia.pdf) that lists specifications for multiple related part numbers.

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Full PDF Text Transcription

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74AHC74; 74AHCT74 Dual D-type flip-flop with set and reset; positive-edge trigger Rev. 8 — 22 April 2020 Product data sheet 1. General description The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC74; 74AHCT74 is a dual positive-edge triggered, D-type flip-flop with individual data inputs (D), clock inputs (CP), set inputs (SD) and reset inputs (RD). It also has complementary outputs (Q and Q). The set and reset are asynchronous active LOW inputs that operate independent of the clock input. Information on the data input is transferred to the Q output on the LOW to HIGH transition of the clock pulse.
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