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74ALVC162835ADGG - 18-bit registered driver

Download the 74ALVC162835ADGG datasheet PDF. This datasheet also covers the 74ALVC162835A variant, as both devices belong to the same 18-bit registered driver family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74ALVC162835A is an 18-bit universal bus driver.

Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP).

When LE is HIGH, the A to Y data flow is transparent.

Key Features

  • Wide supply voltage range from 1.2 V to 3.6 V.
  • CMOS low-power consumption.
  • Direct interface with TTL levels.
  • Current drive ± 12 mA at 3.0 V.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74ALVC162835A-nexperia.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
74ALVC162835A 18-bit registered driver NXP
74ALVC162835 Low Voltage 18-Bit Universal Bus Driver Fairchild Semiconductor
74ALVC162834A 18-bit registered driver NXP
74ALVC162836A 20-bit registered driver NXP
74ALVC162838 Low Voltage 16-Bit Selectable Register/Buffer Fairchild Semiconductor

Other Datasheets by Nexperia

Part Number Description
74ALVC162835A 18-bit registered driver
74ALVC162834A 18-bit registered driver
74ALVC162834ADGG 18-bit registered driver
74ALVC162836A 20-bit registered driver
74ALVC162836ADGG 20-bit registered driver

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74ALVC162835A 18-bit registered driver with 30 Ω termination resistors; 3-state Rev. 7 — 12 October 2017 Product data sheet 1 General description The 74ALVC162835A is an 18-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). When LE is HIGH, the A to Y data flow is transparent. When LE is LOW and CP is held at LOW or HIGH, the data is latched; on the LOW to HIGH transient of CP the A-data is stored in the latch/flip-flop. When OE is LOW the outputs are active. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latch/ flip-flop.