74ALVC74PW Datasheet | Nexperia

description The 74ALVC74 is a dual positive edge triggered, D-type flip-flop. It has individual data (n D) inputs, clock (n CP) inputs, set (n SD) and (n RD) inputs, and plementary n Q and n Q outputs. The set and reset are asynchronous active LOW inputs that operate independently of the clock input. Information on the data input is transferred to the n Q output on the LOW-to-HIGH transition of the clock pulse. The n D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. 2. Features and benefits - Wide supply voltage range from 1.65 V to 3.6 V - plies with JEDEC standard: - JESD8-7 (1.65 to 1.95 V) - JESD8-5 (2.3 to 2.7 V) - JESD8B (2.7 to 3.6 V) - 3.6 V tolerant inputs/outputs - CMOS low power consumption - Direct interface with TTL levels (2.7 V to 3.6 V) - Power-down mode - Latch-up performance exceeds 250 m A - ESD protection: - HBM JESD22-A114E exceeds 2000 V - MM JESD22-A115-A exceeds 200 V - Specified from -40 °C to +85 °C Nexperia 74ALVC74 Dual D-type flip-flop with set and reset; positive-edge trigger 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74ALVC74D -40 °C to +85 °C 74ALVC74PW -40 °C to +85 °C 74ALVC74BQ -40 °C to +85 °C Name SO14 TSSOP14 DHVQFN14 Description Version plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 plastic thin shrink small outline package; 14 leads; SOT402-1 body width 4.4 mm plastic dual in-line patible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm SOT762-1 4. Functional diagram 4 10 1SD 2SD 2...