74ALVC74 - Dual D-type flip-flop

NXP

74ALVC74 Datasheet Preview — Preview of 74ALVC74 PDF

Datasheet Details

Part number	74ALVC74
Manufacturer	NXP ↗
File Size	103.40 KB
Description	Dual D-type flip-flop
Datasheet	74ALVC74_PhilipsSemiconductors.pdf

74ALVC74 Product details

Description

74ALVC74 The 74ALVC74 is a dual positive-edge triggered, D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs.The set and reset are asynchronous active LOW inputs and operate independently of the clock input.Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse.The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operatio

Features

Wide supply voltage range from 1.65 to 3.6 V.
Complies with JEDEC standard: JESD8-7 (1.65 to 1.95 V) JESD8-5 (2.3 to 2.7 V) JESD8B/JESD36 (2.7 to 3.6 V).
3.6 V tolerant inputs/outputs.
CMOS low power consumption.
Direct interface with TTL levels (2.7 to 3.6 V).
Power-down mode.
Latch-up performance exceeds 250 mA.
ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. QUICK.

📁 74ALVC74 Similar Datasheet

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Published: Apr 3, 2005 |