Datasheet4U Logo Datasheet4U.com

74ALVCH16841DGG - 20-bit bus interface D-type latch

Download the 74ALVCH16841DGG datasheet PDF. This datasheet also covers the 74ALVCH16841 variant, as both devices belong to the same 20-bit bus interface d-type latch family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74ALVCH16841 has two 10-bit D-type latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications.

The two sections of each register are controlled independently by the latch enable (nLE) and output enable (nOE) control gates.

Key Features

  • Wide supply voltage range of 1.2 V to 3.6 V.
  • CMOS low power consumption.
  • Direct interface with TTL levels.
  • Current drive ±24 mA at VCC = 3.0 V.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74ALVCH16841-nexperia.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
74ALVCH16841 20-bit bus interface D-type latch NXP
74ALVCH16843 18-bit bus-interface D-type latch NXP
74ALVCH16821 20-bit bus-interface D-type flip-flop NXP
74ALVCH16823 18-bit bus-interface D-type flip-flop NXP
74ALVCH16825 18-bit buffer/driver NXP

Other Datasheets by Nexperia

Part Number Description
74ALVCH16841 20-bit bus interface D-type latch
74ALVCH16843 18-bit bus-interface D-type latch
74ALVCH16843DGG 18-bit bus-interface D-type latch
74ALVCH16821 20-bit bus-interface D-type flip-flop
74ALVCH16821DGG 20-bit bus-interface D-type flip-flop

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74ALVCH16841 20-bit bus interface D-type latch; 3-state Rev. 3 — 12 September 2018 Product data sheet 1. General description The 74ALVCH16841 has two 10-bit D-type latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. The two sections of each register are controlled independently by the latch enable (nLE) and output enable (nOE) control gates. When nOE is LOW, the data in the registers appears at the outputs. When nOE is HIGH the outputs are in High-impedance OFF state. Operation of the nOE input does not affect the state of the flip-flops. The 74ALVCH16841 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level.