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74AUP1G74-Q100 - Low-power D-type flip-flop

Description

The 74AUP1G74-Q100 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs.

Features

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1).
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C.
  • Wide supply voltage range from 0.8 V to 3.6 V.
  • CMOS low power dissipation.
  • High noise immunity.
  • Overvoltage tolerant inputs to 3.6 V.
  • Low static power consumption; ICC = 0.9 μA (maximum).
  • Latch-up performance exceeds 100 mA per JESD 78 Class II.
  • Low noise overshoot and undershoot < 10.

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Full PDF Text Transcription

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74AUP1G74-Q100 Low-power D-type flip-flop with set and reset; positive-edge trigger Rev. 3 — 20 June 2022 Product data sheet 1. General description The 74AUP1G74-Q100 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF.
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