74AUP2G00-Q100 Datasheet | Nexperia

description The 74AUP2G00-Q100 provides dual 2-input NAND function. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits - Automotive product qualification in accordance with AEC-Q100 (Grade 1) - Specified from -40 °C to +85 °C and from -40 °C to +125 °C - Wide supply voltage range from 0.8 V to 3.6 V - High noise immunity - plies with JEDEC standards: - JESD8-12 (0.8 V to 1.3 V) - JESD8-11 (0.9 V to 1.65 V) - JESD8-7 (1.2 V to 1.95 V) - JESD8-5 (1.8 V to 2.7 V) - JESD8-B (2.7 V to 3.6 V) - ESD protection: - HBM JESD22-A114F Class 3A exceeds 5000 V - MM JESD22-A115-A exceeds 200 V - MIL-STD-883, method 3015 Class 3A exceeds 5000 V - Low static power consumption; ICC = 0.9 μA (maximum) - Latch-up performance exceeds 100 m A per JESD78 Class II - Inputs accept voltages up to 3.6 V - Low noise overshoot and undershoot < 10 % of VCC - IOFF circuitry provides partial power-down mode operation 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP2G00DC-Q100 -40 °C to +125 °C VSSOP8 plastic very thin shrink small outline package; 8 leads; SOT765-1 body width 2.3 mm Nexperia Low-power dual 2-input NAND gate 4. Marking Table 2. Marking codes Type number 74AUP2G00DC-Q100 Marking code[1] p00 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking...