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74AUP2G80 - Low-power dual D-type flip-flop

General Description

The 74AUP2G80 provides the dual positive-edge triggered D-type flip-flop.

Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse.

The input pin D must be stable one setup time prior to the LOW-to-HIGH clock transition for predictable operation.

Key Features

  • Wide supply voltage range from 0.8 V to 3.6 V.
  • High noise immunity.
  • Complies with JEDEC standards:.
  • JESD8-12 (0.8 V to 1.3 V).
  • JESD8-11 (0.9 V to 1.65 V).
  • JESD8-7 (1.2 V to 1.95 V).
  • JESD8-5 (1.8 V to 2.7 V).
  • JESD8-B (2.7 V to 3.6 V).
  • ESD protection:.
  • HBM JESD22-A114F Class 3A exceeds 5 000 V.
  • MM JESD22-A115-A exceeds 200 V.
  • CDM JESD22-C101E exceeds 1 000 V.
  • Low static power consu.

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Datasheet Details

Part number 74AUP2G80
Manufacturer Nexperia
File Size 274.87 KB
Description Low-power dual D-type flip-flop
Datasheet download datasheet 74AUP2G80 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74AUP2G80 Low-power dual D-type flip-flop; positive-edge trigger Rev. 11 — 7 December 2020 Product data sheet 1. General description The 74AUP2G80 provides the dual positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The input pin D must be stable one setup time prior to the LOW-to-HIGH clock transition for predictable operation. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF.