74AUP2G80 Description
The 74AUP2G80 provides the dual positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The input pin D must be stable one setup time prior to the LOW-to-HIGH clock transition for predictable operation.
74AUP2G80 Key Features
- Wide supply voltage range from 0.8 V to 3.6 V
- High noise immunity
- plies with JEDEC standards
- JESD8-12 (0.8 V to 1.3 V)
- JESD8-11 (0.9 V to 1.65 V)
- JESD8-7 (1.2 V to 1.95 V)
- JESD8-5 (1.8 V to 2.7 V)
- JESD8-B (2.7 V to 3.6 V)
- ESD protection
- HBM JESD22-A114F Class 3A exceeds 5 000 V
74AUP2G80 Applications
- Wide supply voltage range from 0.8 V to 3.6 V