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74HC158D - Quad 2-input multiplexer

Download the 74HC158D datasheet PDF. This datasheet also covers the 74HC158 variant, as both devices belong to the same quad 2-input multiplexer family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74HC158 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL).

The 74HC158 is specified in compliance with JEDEC standard no.

7A.

Key Features

  • Low-power dissipation.
  • Inverting data path.
  • Complies with JEDEC standard no. 7A.
  • ESD protection:.
  • HBM JESD22-A114F exceeds 2 000 V.
  • MM JESD22-A115-A exceeds 200 V.
  • Multiple package options.
  • Specified from.
  • 40° C to +85 °C and.
  • 40 °C to +125 °C Nexperia 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74HC158D 40 C to +125 C Name SO16 4. Functional diagram 74HC158 Quad 2-input multiple.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74HC158-nexperia.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number 74HC158D
Manufacturer Nexperia
File Size 683.63 KB
Description Quad 2-input multiplexer
Datasheet download datasheet 74HC158D Datasheet

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Other Datasheets by Nexperia

Part Number Description
74HC158 Quad 2-input multiplexer
74HC151 8-input multiplexer
74HC151-Q100 8-input multiplexer
74HC151D 8-input multiplexer
74HC151DB 8-input multiplexer

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74HC158 Quad 2-input multiplexer; inverting Rev. 4 — 23 December 2015 Product data sheet 1. General description The 74HC158 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC158 is specified in compliance with JEDEC standard no. 7A. The 74HC158 is a quad 2-input multiplexer which select 4 bits of data from two sources and are controlled by a common data select input (S). The four outputs present the selected data in the inverted form. The enable input (E) is active LOW. When E is HIGH, all the outputs (1Y to 4Y) are forced HIGH regardless of all other input conditions. Moving the data from two groups of registers to four common output buses is a common use of the 74HC158.