74HC4024 Datasheet - nexperia

7-stage binary ripple counter

74HC4024 Features

* Low-power dissipation

* Complies with JEDEC standard no. 7A

* CMOS input levels

* ESD protection:

* HBM JESD22-A114F exceeds 2 000 V

* MM JESD22-A115-A exceeds 200 V.

* Specified from -40 °C to +80 °C and from -40 °C

74HC4024 General Description

The 74HC4024 is a 7-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to Q6). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LO.

74HC4024 Datasheet (207.82 KB)