74HC73D flip-flop equivalent, dual jk flip-flop.
* CMOS low-power dissipation
* Wide supply voltage range from 2.0 to 6.0 V
* High noise immunity
* Latch-up performance exceeds 100 mA per JESD 78 Class I.
The 74HC73 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for pre.
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