74HC73
description
The 74HC73 is a dual negative edge triggered JK flip-flop with individual J, K, clock (n CP) and reset (n R) inputs and plementary n Q and n Q outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. (n R) is asynchronous, when LOW it overrides the clock and data inputs, forcing the n Q output LOW and the n Q output HIGH. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
2. Features and benefits
- CMOS low-power dissipation
- Wide supply voltage range from 2.0 to 6.0 V
- High noise immunity
- Latch-up performance exceeds 100 m A per JESD 78 Class II Level B
- plies with JEDEC standards
- JESD8C (2.7 V to 3.6 V)
- JESD7A (2.0 V to 6.0 V)
- ESD protection:
- HBM JESD22-A114F exceeds 2000 V
- MM JESD22-A115-A exceeds 200 V
-...
