74HC73 Datasheet (nexperia) - Dual JK flip-flop

74HC73, Dual JK flip-flop

The 74HC73 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs.

The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation.

(nR) is asynchronous, when LOW

74HC73 Features

* CMOS low-power dissipation

* Wide supply voltage range from 2.0 to 6.0 V

* High noise immunity

* Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

* Complies with JEDEC standards

* JESD8C (2.7 V to 3.6 V)

* JESD7A (2.0 V to 6.0