74HC85 Datasheet | Nexperia

74HC85; 74HCT85 4-bit magnitude parator Rev. 4 - 4 August 2021 Product data sheet 1. General description The 74HC85; 74HCT85 is a 4-bit magnitude parator that can be expanded to almost any length. They perform parison of two 4-bit binary, BCD or other monotonic codes and present the three possible magnitude results at the outputs (QA>B, QA=B and QA<B). The 4-bit inputs are weighted (A0 to A3 and B0 to B3), where A3 and B3 are the most significant bits. For proper pare operation the expander inputs (IA>B, IA=B and IA<B) to the least significant position must be connected as follows: IA<B = IA>B = LOW and IA=B = HIGH. For words greater than 4-bits, units can be cascaded by connecting outputs QA>B, QA=B and QA<B to the corresponding inputs of the significant parator. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits - Wide supply voltage range from 2.0 to 6.0 V - CMOS low power dissipation - High noise immunity - Latch-up performance exceeds 100 m A per JESD 78 Class II Level B - Input levels: - For 74HC85: CMOS level - For 74HCT85: TTL level - plies with JEDEC standards: - JESD8C (2.7 V to 3.6 V) - JESD7A (2.0 V to 6.0 V) - ESD protection: - HBM JESD22-A114-A exceeds 2000 V - MM JESD22-A115-A exceeds 200 V - Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Applications - Process controllers - Servo-motor control 4. Ordering information Table 1. Ordering information Type number Package Temperature range 74HC85D - 40 °C to +125...