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74HCT109-Q100 - Dual JK flip-flop

Download the 74HCT109-Q100 datasheet PDF (74HC109-Q100 included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for dual jk flip-flop.

Description

The 74HC109-Q100; 74HCT109-Q100 is a dual positive edge triggered JK flip-flop featuring individual nJ and nK inputs.

It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and complementary nQ and nQ outputs.

Features

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1).
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C.
  • Input levels:.
  • For 74HC109-Q100: CMOS level.
  • For 74HCT109-Q100: TTL level.
  • J and K inputs for easy D-type flip-flop.
  • Toggle flip-flop or "do nothing" mode.
  • Specified in compliance with JEDEC standard no. 7A.
  • ESD protection:.
  • MIL-STD-883, method 3015 exceeds 2000 V.
  • HB.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74HC109-Q100-nexperia.pdf) that lists specifications for multiple related part numbers.

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Full PDF Text Transcription

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74HC109-Q100; 74HCT109-Q100 Dual JK flip-flop with set and reset; positive-edge-trigger Rev. 2 — 1 April 2020 Product data sheet 1. General description The 74HC109-Q100; 74HCT109-Q100 is a dual positive edge triggered JK flip-flop featuring individual nJ and nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The nJ and nK inputs control the state changes of the flip-flops as described in the mode select function table. The nJ and nK inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.
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