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74HCT165D - 8-bit parallel-in/serial out shift register

Download the 74HCT165D datasheet PDF. This datasheet also covers the 74HC165 variant, as both devices belong to the same 8-bit parallel-in/serial out shift register family and are provided as variant models within a single manufacturer datasheet.

Description

The 74HC165; 74HCT165 are 8-bit serial or parallel-in/serial-out shift registers.

Features

  • Wide supply voltage range from 2.0 V to 6.0 V.
  • CMOS low power dissipation.
  • High noise immunity.
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.
  • Asynchronous 8-bit parallel load.
  • Synchronous serial input.
  • Input levels:.
  • For 74HC165: CMOS level.
  • For 74HCT165: TTL level.
  • Complies with JEDEC standards:.
  • JESD8C (2.7 V to 3.6 V).
  • JESD7A (2.0 V to 6.0 V).
  • ESD protectio.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74HC165-nexperia.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number 74HCT165D
Manufacturer Nexperia
File Size 317.10 KB
Description 8-bit parallel-in/serial out shift register
Datasheet download datasheet 74HCT165D Datasheet

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Other Datasheets by Nexperia

Part Number Description
74HCT165 8-bit parallel-in/serial out shift register
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74HC165; 74HCT165 8-bit parallel-in/serial out shift register Rev. 8 — 9 May 2025 Product data sheet 1. General description The 74HC165; 74HCT165 are 8-bit serial or parallel-in/serial-out shift registers. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and two complementary serial outputs (Q7 and Q7). When the parallel load input (PL) is LOW the data from D0 to D7 is loaded into the shift register asynchronously. When PL is HIGH data enters the register serially at DS. When the clock enable input (CE) is LOW data is shifted on the LOW-to-HIGH transitions of the CP input. A HIGH on CE will disable the CP input. Inputs are overvoltage tolerant to 15 V. This enables the device to be used in HIGH-to-LOW level shifting applications. 2.
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