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74HCT165 - 8-bit parallel-in/serial out shift register

Download the 74HCT165 datasheet PDF (74HC165 included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for 8-bit parallel-in/serial out shift register.

Description

The 74HC165; 74HCT165 are high-speed Si-gate CMOS devices that comply with JEDEC standard no.

7A.

They are pin compatible with Low-power Schottky TTL (LSTTL).

Features

  • I Asynchronous 8-bit parallel load I Synchronous serial input I Complies with JEDEC standard no. 7A I ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V I Specified from.
  • 40 °C to +85 °C and from.
  • 40 °C to +125 °C 3.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74HC165-NXP.pdf) that lists specifications for multiple related part numbers.

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Full PDF Text Transcription

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74HC165; 74HCT165 8-bit parallel-in/serial out shift register Rev. 03 — 14 March 2008 Product data sheet 1. General description The 74HC165; 74HCT165 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL). The 74HC165; 74HCT165 are 8-bit parallel-load or serial-in shift registers with complementary serial outputs (Q7 and Q7) available from the last stage. When the parallel load (PL) input is LOW, parallel data from the D0 to D7 inputs are loaded into the register asynchronously. When PL is HIGH, data enters the register serially at the DS input and shifts one place to the right (Q0 → Q1 → Q2, etc.) with each positive-going clock transition.
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