74HCT138 Overview
74HCT138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7).
74HCT138 Key Features
- plies with JEDEC standard no. 7A
- Input levels
- For 74HC138: CMOS level
- For 74HCT138: TTL level
- Demultiplexing capability
