74HCT137 Datasheet | Texas Instruments

Features - Select One of Eight Data Outputs - Active Low for CD74HC137 and CD74HCT137 - Active High for ’HC237 and CD74HCT237 - l/O Port or Memory Selector - Two Enable Inputs to Simplify Cascading - Typical Propagation Delay of 13ns 15p F, TA = 25o C (CD74HC237) at = 5V, - Fanout (Over Temperature Range) - Standard Outputs - - - 10 LSTTL Loads - Bus Driver Outputs - - . . . 15 LSTTL Loads - Wide Operating Temperature Range . . . -55o C to 125o C - Balanced Propagation Delay and Transition Times - Significant Power Reduction pared to LSTTL Logic ICs - HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30%, of VCC at VCC = 5V - HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic patibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input patibility, Il ≤ 1µA at VOL, VOH Description Both circuits have three binary select inputs (A0, A1 and A2) that can be latched by an active High Latch Enable (LE) signal to isolate the outputs from select-input changes. A “Low” LE makes the output transparent to the input and the circuit functions as a one-of-eight decoder. Two Output Enable inputs (OE1 and OE0) are provided to simplify cascading and to facilitate demultiplexing. The demultiplexing function is acplished by using the A0, A1, A2 inputs to select the desired output and using one of the other Output Enable inputs as the data input while holding the other Output Enable input in its active state. In the CD74HC137 and CD74HCT137 the selected output is a “Low”; in the ’HC237 and CD74HCT237 the selected output is a “High”. Ordering Information PART NUMBER CD54HC237F3A CD74HC137E CD74HC137PW CD74HC137PWR CD74HC137PWT CD74HC237E CD74HC237M CD74HC237MT CD74HC237M96 TEMP. RANGE (o C) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld CERDIP 16 Ld PDIP 16 Ld TSSOP 16 Ld TSSOP 16 Ld TSSOP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld...