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74HCT163 - Presettable synchronous 4-bit binary counter

This page provides the datasheet information for the 74HCT163, a member of the 74HC163 Presettable synchronous 4-bit binary counter family.

Datasheet Summary

Description

The 74HC163; 74HCT163 is a synchronous presettable binary counter with an internal look-head carry.

Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP).

The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW.

Features

  • Complies with JEDEC standard no. 7A.
  • Input levels:.
  • For 74HC163: CMOS level.
  • For 74HCT163: TTL level.
  • Synchronous counting and loading.
  • 2 count enable inputs for n-bit cascading.
  • Synchronous reset.
  • Positive-edge triggered clock.
  • ESD protection:.
  • HBM JESD22-A114F exceeds 2 000 V.
  • MM JESD22-A115-A exceeds 200 V.
  • Multiple package options.
  • Specified from -40 °C to +85 °C and -40 °C t.

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Datasheet preview – 74HCT163

Datasheet Details

Part number 74HCT163
Manufacturer nexperia
File Size 298.21 KB
Description Presettable synchronous 4-bit binary counter
Datasheet download datasheet 74HCT163 Datasheet
Additional preview pages of the 74HCT163 datasheet.

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Full PDF Text Transcription

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74HC163; 74HCT163 Presettable synchronous 4-bit binary counter; synchronous reset Rev. 5 — 12 October 2018 Product data sheet 1. General description The 74HC163; 74HCT163 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action. It causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET).
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