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74HCT193-Q100 - Presettable synchronous 4-bit binary up/down counter

Download the 74HCT193-Q100 datasheet PDF (74HC193-Q100 included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for presettable synchronous 4-bit binary up/down counter.

Description

The 74HC193-Q100; 74HCT193-Q100 is a 4-bit synchronous binary up/down counter.

Separate up/down clocks, CPU and CPD respectively, simplify operation.

The outputs change state synchronously with the LOW-to-HIGH transition of either clock input.

Features

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1).
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C.
  • Wide supply voltage range from 2.0 to 6.0 V.
  • CMOS low power dissipation.
  • High noise immunity.
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.
  • Input levels:.
  • For 74HC193-Q100: CMOS level.
  • For 74HCT193-Q100: TTL level.
  • Synchronous reversible 4-bit binary counti.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74HC193-Q100-nexperia.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number 74HCT193-Q100
Manufacturer nexperia
File Size 325.42 KB
Description Presettable synchronous 4-bit binary up/down counter
Datasheet download datasheet 74HCT193-Q100 Datasheet

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Full PDF Text Transcription

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74HC193-Q100; 74HCT193-Q100 Presettable synchronous 4-bit binary up/down counter Rev. 3 — 8 September 2021 Product data sheet 1. General description The 74HC193-Q100; 74HCT193-Q100 is a 4-bit synchronous binary up/down counter. Separate up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is pulsed while CPD is held HIGH, the device counts up. If the CPD clock is pulsed while CPU is held HIGH, the device counts down. Only one clock input can be held HIGH at any time to guarantee predictable behavior. The device can be cleared at any time by the asynchronous master reset input (MR).
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