Datasheet4U Logo Datasheet4U.com

74HCT273-Q100 - Octal D-type flip-flop

Download the 74HCT273-Q100 datasheet PDF (74HC273-Q100 included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for octal d-type flip-flop.

Description

The 74HC273-Q100; 74HCT273-Q100 is an octal positive-edge triggered D-type flip-flop.

Features

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1).
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C.
  • Wide supply voltage range from 2.0 V to 6.0 V.
  • CMOS low power dissipation.
  • High noise immunity.
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.
  • Complies with JEDEC standards:.
  • JESD8C (2.7 V to 3.6 V).
  • JESD7A (2.0 V to 6.0 V).
  • Input levels:.
  • For 74HC2.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74HC273-Q100-nexperia.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

  • 74HCT273-Q100 - Octal D-type flip-flop (NXP)
  • 74HCT273 - Octal D-type flip-flop (NXP)
  • 74HCT27 - Triple 3-input NOR gate (NXP)
  • 74HCT20 - Dual 4-input NAND gate (Philips)
  • 74HCT21 - Dual 4-input AND gate (Philips)
  • 74HCT221 - Dual non-retriggerable monostable multivibrator (Philips)
  • 74HCT237 - 3-to-8 line decoder/demultiplexer (Philips)
  • 74HCT237 - High-Speed CMOS Logic 3 to 8-Line Decoder/Demultiplexer (Texas Instruments)
  • 74HCT238 - 3-to-8 line decoder/demultiplexer (Philips)
  • 74HCT240 - Octal buffer/line driver (Philips)
Other Datasheets by nexperia

Full PDF Text Transcription

Click to expand full text
74HC273-Q100; 74HCT273-Q100 Octal D-type flip-flop with reset; positive-edge trigger Rev. 2 — 3 September 2020 Product data sheet 1. General description The 74HC273-Q100; 74HCT273-Q100 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently of clock and data inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Published: |