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74HCT280D Datasheet Preview

74HCT280D Datasheet

9-bit odd/even parity generator/checker

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74HC280; 74HCT280
9-bit odd/even parity generator/checker
Rev. 3 — 15 September 2016
Product data sheet
1. General description
The 74HC280; 74HCT280 is a 9-bit parity generator or checker. Both even and odd parity
outputs are available. The even parity output (PE) is HIGH when an even number of data
inputs (I0 to I8) is HIGH. The odd parity output (PO) is HIGH when an odd number of data
inputs are HIGH. Expansion to larger word sizes is accomplished by tying the even
outputs (PE) of up to nine parallel devices to the final stage data inputs. Inputs include
clamp diodes. It enables the use of current limiting resistors to interface inputs to voltages
in excess of VCC.
2. Features and benefits
Complies with JEDEC standard no. 7A
Input levels:
For 74HC280: CMOS level
For 74HCT280: TTL level
Word-length easily expanded by cascading
Generates either odd or even parity for nine data bits
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Specified from 40 C to +85 C and 40 C to +125 C
3. Ordering information
Table 1. Ordering information
Type number
Temperature
range
74HC280D
40 C to +125 C
74HCT280D
74HCT280DB 40 C to +125 C
Name
SO14
SSOP14
Description
Version
plastic small outline package; 14 leads; body width
3.9 mm
plastic shrink small outline package; 14 leads; body
width 5.3 mm
SOT108-1
SOT337-1




nexperia

74HCT280D Datasheet Preview

74HCT280D Datasheet

9-bit odd/even parity generator/checker

No Preview Available !

Nexperia
4. Functional diagram
Fig 1. Logic symbol
74HC280; 74HCT280
9-bit odd/even parity generator/checker
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3( 
32 
DDD
,
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Fig 2. Logic diagram
74HC_HCT280
Product data sheet
32
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 15 September 2016
DDD
.
2 of 15
© Nexperia B.V. 2017. All rights reserved


Part Number 74HCT280D
Description 9-bit odd/even parity generator/checker
Maker nexperia
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74HCT280D Datasheet PDF






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