74HCT377D Datasheet | Nexperia

description The 74HC377; 74HCT377 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. Input E must be stable one set-up time prior to the LOW-to-HIGH transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits - Wide supply voltage range from 2.0 V to 6.0 V - CMOS low power dissipation - High noise immunity - Latch-up performance exceeds 100 m A per JESD 78 Class II Level B - plies with JEDEC standards: - JESD8C (2.7 V to 3.6 V) - JESD7A (2.0 V to 6.0 V) - mon clock and master reset - Eight positive edge-triggered D-type flip-flops - Input levels: - For 74HC377: CMOS level - For 74HCT377: TTL level - ESD protection: - HBM JESD22-A114F exceeds 2000 V - MM JESD22-A115-A exceeds 200 V. - Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description 74HC377D -40 °C to +85 °C SO20 plastic small outline package; 20 leads; body width 7.5 mm 74HC377PW -40 °C to +85 °C 74HCT377PW TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm Version SOT163-1 SOT360-1 Nexperia 4. Functional diagram 74HC377; 74HCT377 Octal D-type flip-flop with data enable; positive-edge trigger Fig. 1. Functional diagram 3 D0 4 D1 7 D2 8 D3 FF1 13 D4 to FF8 14 D5 17...