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74LVC138A - 3-to-8 line decoder/demultiplexer

Description

The 74LVC138A decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7).

Features

  • Overvoltage tolerant inputs to 5.5 V.
  • Wide supply voltage range from 1.2 V to 3.6 V.
  • CMOS low power consumption.
  • Direct interface with TTL levels.
  • Demultiplexing capability.
  • Multiple input enable for easy expansion.
  • Ideal for memory chip select decoding.
  • Mutually exclusive outputs.
  • Output drive capability 50 Ω transmission lines at 125 °C.
  • Complies with JEDEC standard:.
  • JESD8-7A (1.65 V to 1.95 V).

📥 Download Datasheet

Datasheet Details

Part number 74LVC138A
Manufacturer nexperia
File Size 253.92 KB
Description 3-to-8 line decoder/demultiplexer
Datasheet download datasheet 74LVC138A Datasheet

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Full PDF Text Transcription

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74LVC138A 3-to-8 line decoder/demultiplexer; inverting Rev. 8 — 20 September 2021 Product data sheet 1. General description The 74LVC138A decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The 74LVC138A features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion of the 74LVC138A to a 1-of-32 (5 to 32 lines) decoder with just four 74LVC138A ICs and one inverter. The 74LVC138A can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Inputs can be driven from either 3.3 V or 5 V devices.
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