74LVC1G175 Description
The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR) is an asynchronous active LOW input and operates independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse.
74LVC1G175 Key Features
- Wide supply voltage range from 1.65 V to 5.5 V
- High noise immunity
- Overvoltage tolerant inputs to 5.5 V
- ±24 mA output drive (VCC = 3.0 V)
- CMOS low power dissipation
- Direct interface with TTL levels
- IOFF circuitry provides partial Power-down mode operation
- Latch-up performance exceeds 250 mA
- plies with JEDEC standard
- JESD8-7 (1.65 V to 1.95 V)
74LVC1G175 Applications
- Wide supply voltage range from 1.65 V to 5.5 V