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74LVT02 - 3.3V Quad 2-input NOR gate

Description

The 74LVT02 is a quad 2-input NOR gate.

This device is fully specified for partial power down applications using IOFF.

The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features

  • Wide supply voltage range from 2.7 V to 3.6 V.
  • Output capability: +64 mA and -32 mA.
  • Direct interface with TTL levels.
  • Overvoltage tolerant inputs to 5.5 V.
  • Power-up 3-state.
  • No bus current loading when output is tied to 5 V bus.
  • IOFF circuitry provides partial Power-down mode operation.
  • Latch-up performance exceeds 500 mA per JESD 78 Class II Level B.
  • Complies with JEDEC standards:.
  • JESD8C (2.7 V to 3.6 V.

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Datasheet Details

Part number 74LVT02
Manufacturer nexperia
File Size 206.18 KB
Description 3.3V Quad 2-input NOR gate
Datasheet download datasheet 74LVT02 Datasheet

Full PDF Text Transcription

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74LVT02 3.3 V Quad 2-input NOR gate Rev. 4 — 1 March 2021 Product data sheet 1. General description The 74LVT02 is a quad 2-input NOR gate. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits • Wide supply voltage range from 2.7 V to 3.6 V • Output capability: +64 mA and -32 mA • Direct interface with TTL levels • Overvoltage tolerant inputs to 5.5 V • Power-up 3-state • No bus current loading when output is tied to 5 V bus • IOFF circuitry provides partial Power-down mode operation • Latch-up performance exceeds 500 mA per JESD 78 Class II Level B • Complies with JEDEC standards: • JESD8C (2.
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