Datasheet4U Logo Datasheet4U.com

HEF4014B - 8-bit static shift register

Description

The HEF4014B is a fully synchronous edge-triggered 8-bit static shift register with eight synchronous parallel inputs (D0 to D7), a synchronous serial data input (DS), a synchronous parallel enable input (PE), a LOW-to-HIGH edge-triggered clock input (CP) and buffered parallel outputs from the last

Features

  • Tolerant of slow clock rise and fall times.
  • Fully static operation.
  • 5 V, 10 V, and 15 V parametric ratings.
  • Standardized symmetrical output characteristics.
  • Specified from -40 °C to +85 °C.
  • Complies with JEDEC standard JESD 13-B 3.

📥 Download Datasheet

Datasheet Details

Part number HEF4014B
Manufacturer nexperia
File Size 193.96 KB
Description 8-bit static shift register
Datasheet download datasheet HEF4014B Datasheet

📁 Similar Datasheet

  • HEF4014B - 8-bit static shift register (NXP)
  • HEF4014B - 8-bit static shift register (Philips)
  • HEF40106B - Hex inverting Schmitt trigger (NXP)
  • HEF40106B - Hex inverting Schmitt trigger (Philips)
  • HEF4011B - Quadruple 2-input NAND gate (NXP)
  • HEF4011B - Quadruple 2-input NAND gate (Philips)
  • HEF4011UB - Quadruple 2-input NAND gate (NXP)
  • HEF4012B - Dual 4-input NAND gate (NXP)
  • HEF4013B - Dual D-type flip-flop (NXP)
  • HEF4015B - Dual 4-bit static shift register (NXP)
Other Datasheets by nexperia

Full PDF Text Transcription

Click to expand full text
HEF4014B 8-bit static shift register Rev. 10 — 17 October 2018 Product data sheet 1. General description The HEF4014B is a fully synchronous edge-triggered 8-bit static shift register with eight synchronous parallel inputs (D0 to D7), a synchronous serial data input (DS), a synchronous parallel enable input (PE), a LOW-to-HIGH edge-triggered clock input (CP) and buffered parallel outputs from the last three stages (Q5 to Q7). Operation is synchronous and the device is edge-triggered on the LOW-to-HIGH transition of CP. Each register stage is of a D-type master-slave flip-flop type. When PE is HIGH, data is loaded into the register from D0 to D7 on the LOW-to-HIGH transition of CP.
Published: |