Datasheet4U Logo Datasheet4U.com

HEF4015B - Dual 4-bit static shift register

Description

The HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel converter).

Each shift register has a serial data input (nD), a clock input (nCP), four fully buffered parallel outputs (Q0 to Q3) and an overriding asynchronous master reset input (nMR).

Features

  • Wide supply voltage range from 3.0 V to 15.0 V.
  • CMOS low power dissipation.
  • High noise immunity.
  • Tolerant of slow clock rise and fall times.
  • Fully static operation.
  • 5 V, 10 V, and 15 V parametric ratings.
  • Standardized symmetrical output characteristics.
  • Complies with JEDEC standard JESD 13-B.
  • ESD protection:.
  • HBM JESD22-A114F exceeds 2000 V.
  • MM JESD22-A115-B exceeds 200 V.
  • Specified from.

📥 Download Datasheet

Datasheet Details

Part number HEF4015B
Manufacturer nexperia
File Size 208.73 KB
Description Dual 4-bit static shift register
Datasheet download datasheet HEF4015B Datasheet

📁 Similar Datasheet

  • HEF4015B - Dual 4-bit static shift register (NXP)
  • HEF40106B - Hex inverting Schmitt trigger (NXP)
  • HEF40106B - Hex inverting Schmitt trigger (Philips)
  • HEF4011B - Quadruple 2-input NAND gate (NXP)
  • HEF4011B - Quadruple 2-input NAND gate (Philips)
  • HEF4011UB - Quadruple 2-input NAND gate (NXP)
  • HEF4012B - Dual 4-input NAND gate (NXP)
  • HEF4013B - Dual D-type flip-flop (NXP)
  • HEF4014B - 8-bit static shift register (NXP)
  • HEF4014B - 8-bit static shift register (Philips)
Other Datasheets by nexperia

Full PDF Text Transcription

Click to expand full text
HEF4015B Dual 4-bit static shift register Rev. 10 — 26 November 2021 Product data sheet 1. General description The HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel converter). Each shift register has a serial data input (nD), a clock input (nCP), four fully buffered parallel outputs (Q0 to Q3) and an overriding asynchronous master reset input (nMR). Information present on nD is shifted to the first register position, and all the data in the register is shifted one position to the right on the LOW-to-HIGH transition of nCP. A HIGH on nMR clears the register and forces Q0 to Q3 to LOW, independent of nCP and nD. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VDD. 2.
Published: |