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HEF4020B - 14-stage binary counter

Datasheet Summary

Description

The HEF4020B is a 14-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and 12 buffered parallel outputs (Q0, and Q3 to Q13).

The counter advances on the HIGH-to-LOW transition of CP.

Features

  • Wide supply voltage range from 3.0 V to 15.0 V.
  • CMOS low power dissipation.
  • High noise immunity.
  • High speed operation.
  • Fully static operation.
  • 5 V, 10 V, and 15 V parametric ratings.
  • Standardized symmetrical output characteristics.
  • Complies with JEDEC standard JESD 13-B.
  • ESD protection:.
  • HBM JESD22-A114F exceeds 2000 V.
  • MM JESD22-A115-B exceeds 200 V.
  • Specified from -40 °C to +85 °C 3. O.

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Datasheet preview – HEF4020B

Datasheet Details

Part number HEF4020B
Manufacturer nexperia
File Size 212.35 KB
Description 14-stage binary counter
Datasheet download datasheet HEF4020B Datasheet
Additional preview pages of the HEF4020B datasheet.

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Full PDF Text Transcription

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HEF4020B 14-stage binary counter Rev. 11 — 7 December 2021 Product data sheet 1. General description The HEF4020B is a 14-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and 12 buffered parallel outputs (Q0, and Q3 to Q13). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VDD. 2. Features and benefits • Wide supply voltage range from 3.0 V to 15.
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