DESCRIPTION
A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. A feature of the HEF4020B is: high speed (typ. 35 MHz at VDD = 15 V). HEF4020B MSI Fig.1 Functional diagram. HEF4020BP(N): HEF4020BD(F): HEF4020BT(D): 16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America PINNING Fig.2 Pinning diagram. CP MR O0, O3 to O13 clock input (HIGH to LOW edge triggered) master reset input (active HIGH) parallel outputs FAMILY DATA, IDD LIMITS category MSI See Family Specifications January 1995 2 Philips Semiconductors Product specification 14-stage binary counter HEF4020B MSI Fig.3 Logic diagram. January 1995 3 Philips Semiconductors Product specification 14-stage binary counter AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns; see also waveforms Fig.4 VDD V Propagation delays CP → Ο0...
NXP Semiconductors
