HEF4520BT
description
The HEF4520B is a dual 4-bit internally synchronous binary counter with two clock inputs (n CP0 and n CP1), buffered outputs from all four bit positions (n Q0 to n Q3) and an asynchronous master reset input (n MR). The counter advances on either the LOW-to-HIGH transition of n CP0 if n CP1 is HIGH or the HIGH-to-LOW transition of n CP1 if n CP0 is LOW. Either n CP0 or n CP1 may be used as the clock input to the counter and the other clock input may be used as a clock enable input. A HIGH on n MR resets the counter (n Q0 to n Q3 = LOW) independent of n CP0 and n CP1. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VDD.
2. Features and benefits
- Tolerant of slow clock rise and fall times
- Fully static operation
- 5 V, 10 V, and 15 V parametric ratings
- Wide supply voltage range from 3.0 V to 15.0 V
- CMOS low power dissipation
- High noise immunity
- Standardized symmetrical output characteristics
- plies with...
