US5D308 translator equivalent, 8-output ultra-low additive jitter differential clock buffer/level translator.
* Two differential reference clock input pairs
* Differential input pairs can accept the following differential input
levels: LVPECL, LVDS, HCSL, HSTL or Single E.
* Clock distribution and level translation for ADCs, DACs, Multi-
Gigabit Elthernet, XAUI, Fibre channel, SATA/SAS, .
The US5D308 is a 2.1-Ghz,8-output differential high-performance clock fanout buffer.
The input clock can be selected from two differential inputs or one crystal input. The selected input clock is distributed to two banks of 4 differential outputs and.
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