53C96 Datasheet - AMD

53C96 AM53C96

The High Performance SCSI Controller (HPSC) has a flexible three bus architecture. The HPSC has a 16-bit DMA interface, an 8 bit host data interface and an 8-bit SCSI data interface. The HPSC is designed to minimize host intervention by implementing common SCSI sequences in hardware. An on-chip stat.

PRELIMINARY Am53C94/Am53C96 High Performance SCSI Controller DISTINCTIVE CHARACTERISTICS s s s s s s s s s Pin/function compatible with NCR53C94/53C96 AMD’s Patented GLITCH EATERTM Circuitry on REQ and ACK inputs 5 Mbytes per second synchronous SCSI transfer rate 20 Mbytes per second DMA transfer rate 16-bit DMA Interface plus 2 bits of parity Flexible three bus architecture Single ended SCSI bus supported by Am53C94 Single ended and differential SCSI bus supported by Am53C96 Selection of multi.

53C96 Features

* C/D TSEL I/O

* I/O + I/O SDC 1 SD 1

* SD 0 + SD 0 SDC 0 SD 0 AMD 75ALS170 ISEL ATN

* ATN + ATN SDC 2 SD 2

* SD 1 + SD 1

* SD 2 + SD 2

53C96 Datasheet (353.34 KB)