ITAx is a family of non-inverting internal tristate buffers with active low enable. Logic Symbol Truth Table ITAx EN AQ EN AQ EN A Q HXZ LLL L HH Z = High Impedance HDL Syntax Verilog ITAx inst_name (Q, A, EN); VHDL inst_name: ITAx port map (Q, A, EN); Pin Loading Pin Name A EN Q ITA1 1.0 1..
