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ATLV35 - Ultra Low Voltage Gate Arrays

This page provides the datasheet information for the ATLV35, a member of the ATLV Ultra Low Voltage Gate Arrays family.

Datasheet Summary

Description

The ATLV Series CMOS gate arrays employ 1.0 µ-drawn, double-level metal, Si-gate, CMOS technology processed in Atmel's U.S.-based, advanced manufacturing facility.

The arrays utilize an enhanced channelless architecture which results in greater than 50 percent usable gates.

Features

  • Specifically Designed for Battery Powered.

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Datasheet preview – ATLV35

Datasheet Details

Part number ATLV35
Manufacturer ATMEL Corporation
File Size 88.75 KB
Description Ultra Low Voltage Gate Arrays
Datasheet download datasheet ATLV35 Datasheet
Additional preview pages of the ATLV35 datasheet.

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Full PDF Text Transcription

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ATLV Features Specifically Designed for Battery Powered Applications 1.0 - 3.0 Volts and will Operate from 0.7 to 5.5 Volts • Static Current Drain of <75 nA at 1.0 Volts • 200 MHz Maximum Toggle Frequency for Flip Flop at 1.5 Volts • 1.0 µ Drawn Gate Length CMOS Gate Arrays • All Package Styles Offered Including TQFP and TAB • Improved Product Testability Using Serial Scan, Boundary Scan, www.datasheet4u.com and JTAG • Second Source Existing ASIC Design in Atmel's ATLV via Design Translation. Improved Performance and Lower Cost • Description The ATLV Series CMOS gate arrays employ 1.0 µ-drawn, double-level metal, Si-gate, CMOS technology processed in Atmel's U.S.-based, advanced manufacturing facility.
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