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Features
• High Density, High Performance Electrically Erasable Complex Programmable Logic Device – 64 Macrocells – 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell – 44, 68, 84, 100 pins – 7 ns Maximum Pin-to-Pin Delay – Registered Operation Up To 100 MHz – Enhanced Routing Resources
• In-System Programmability (ISP) via JTAG • Flexible Logic Macrocell
– D/T/Latch Configurable Flip Flops – Global and Individual Register Control Signals – Global and Individual Output Enable – Programmable Output Slew Rate – Programmable Output Open Collector Option – Maximum Logic utilization by burying a register within a COM output • Advanced Power Management Features – Automatic 100 µA Stand-By for “Z” Version – Pin-Controlled 4 mA Stand-By Mode (Typical) – Programmable Pin-Keeper Inputs
ATF1504ASZ Datasheet
